Back to the cleanroom

01Start

A layout and a substrate.

Design & MaskLayout review, photomasks, e-beam writing

Substrate & WafersSi, SOI, glass, quartz, sapphire, SiC, GaN

02Clean

A surface ready for the next step.

Wafer CleaningSolvent, piranha, RCA, HF, plasma

03Pattern

Resist openings where this layer goes.

PhotolithographyMask aligner, maskless aligner, e-beam lithography

04Add or remove

Deposit, plate, lift off, or etch through the pattern.

Thin Film DepositionE-beam, thermal, sputter, PECVD, APCVD, ALD, parylene

Lift-Off PatterningUndercut resist stacks, metal lift-off

ElectroplatingCu, Ni, Au, Sn

EtchingRIE, ICP-RIE, wet etching

05Treat

Anneal or oxidize when the stack calls for it.

AnnealingTube furnace, oxidation, RTA

06Finish

Separate the parts and ship them.

Dicing & PackagingBlade dicing, die handling, wire bonding

Standard service

Thin Film Deposition

Metal, dielectric and polymer coatings on wafers, pieces and compatible small components. Select the material, thickness and surfaces that need coverage.

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01 / 07

Electron-Beam Evaporation

Directional metal films for contacts, adhesion stacks and lift-off patterns.

Wafer size: Up to 4"
Ultimate vacuum: ~1.1 × 10⁻⁸ mbar
Substrate heating: Up to 700 °C
Glancing angle: 1 – 355°

Materials

Al
Au
Ti
Ni
Cr
Pt
W
Ag
AuPd
FeCoB

Materials and thickness

Material	Thickness per run	Use and notes
Al	1 nm – 1 µm	Metal layer Source capacity limits thicker runs.
Au	1–600 nm	Metal layer An adhesion layer improves bonding to oxidized Si.
Ti	1 nm – 1 µm	Adhesion or metal layer Source capacity limits thicker runs.
Ni	1 nm – 1 µm	Metal layer Source capacity limits thicker runs.
Cr	1–300 nm	Adhesion or metal layer Stress and flaking limit thicker films.
Pt	1–600 nm	Metal layer Tensile stress and source capacity limit thicker films.
W	1–20 nm	Metal layer Heat limits continuous runs; thicker films need staged deposition or sputtering.
Ag	1 nm – 1 µm	Metal layer Source capacity limits thicker runs.
AuPd	On request	Alloy layer
FeCoB	On request	Magnetic alloy layer

Full specifications

Substrates: Si, glass, fused silica, sapphire and SiC.
Sample size: Pieces to 100 mm wafers.
Ultimate vacuum: On the order of 1.1 × 10⁻⁸ mbar.
Substrate heating: Up to 700 °C on a molybdenum holder; passive cooling through the carrier heatsink.
Glancing-angle deposition: 1–355°, with 0.1° accuracy and reproducibility.
Substrate rotation: Up to 5 RPM.
Radiant heat: Heat from the source can exceed a resist's thermal budget.
Materials: Al, Au, Ti, Ni, Cr, Pt, W, Ag, AuPd and FeCoB.
Conformality: Directional coverage; unsuitable for deep sidewalls and hidden surfaces.
CMOS compatibility: List every existing film, including Au, Cu and polymers; CMOS-clean processing uses a separate material flow.

Ultrathin films can be discontinuous or contain pinholes; electrical continuity depends on material and substrate.
Resist height and undercut limit the metal thickness suitable for lift-off.
Heat-sensitive samples require a maximum allowable temperature and temperature monitoring.
Source capacity and film stress limit the thickness of a single run.
Prior Au, Ag or Cu exposure can restrict later clean deposition and etching; list the complete processing history.

02 / 07

Thermal Evaporation

Metal films for blanket coatings, lift-off patterns and co-evaporated mixes.

Wafer size: Up to 4"
Substrate heating: None
Coverage: Directional
Co-evaporation: 2 sources

Materials

Materials and thickness

Material	Thickness per run	Use and notes
Al	1 nm – 1 µm	Metal layer Source charge limits thick runs.
Cr	10–100 nm	Adhesion layer
Au	1–200 nm	Metal layer Adhesion layer may be needed.
Ag	1–500 nm	Metal layer Films above 200 nm require sufficient source loading.

Full specifications

Substrates: Si, glass, fused silica, sapphire and SiC.
Sample size: Pieces to 100 mm wafers; samples must fit the holder.
Process temperature: No intentional substrate heating; radiant heat can soften resists and polymers.
Materials: Al, Cr, Au and Ag; sequential layers and co-evaporation.
Conformality: Directional deposition for undercut lift-off masks.
CMOS compatibility: List every existing film, including Au, Cu and polymers; CMOS-clean processing uses a separate material flow.

Ultrathin films can be discontinuous or contain pinholes; electrical continuity depends on material and substrate.
Co-evaporated composition depends on the selected materials and source settings; specify the required composition.

03 / 07

Sputtering

Magnetron sputtering of metal, oxide, silicon and phase-change films for blanket coatings and multilayer stacks.

Wafer size: Up to 4"
Ultimate vacuum: ~1.1 × 10⁻⁷ Torr
Modes: DC / RF
Reactive gas: O₂ / N₂

Materials

Ti
W
Fe
Ag
Al
Mo
MgO
WO₃
Al₂O₃
SiO₂
Undoped Si
Ge₂Sb₂Te₅
Sb₂Te₃
GeTe

Materials and thickness

Material	Thickness per run	Use and notes
Ti	5–150 nm	Metal layer
W	1–600 nm	Metal layer
Fe	5–150 nm	Metal layer
Ag	1–200 nm	Metal layer
Al	1–500 nm	Metal layer
Mo	1–100 nm	Metal layer
MgO	On request	Oxide layer
WO₃	5–150 nm	Oxide layer
Al₂O₃	A few nm – 200 nm	Oxide layer Thick deposits can flake; the recipe limits each run.
SiO₂	5–150 nm	Oxide layer Some recipes support 200–300 nm films.
Si (undoped)	A few nm – 200 nm	Silicon layer Some recipes support films above 200 nm.
Ge₂Sb₂Te₅	On request	Phase-change layer
Sb₂Te₃	On request	Phase-change layer
GeTe	On request	Phase-change layer

Full specifications

Substrates: Si, glass, fused silica, sapphire and SiC.
Sample size: Pieces to 100 mm wafers.
Ultimate vacuum: On the order of 1.1 × 10⁻⁷ Torr.
Modes: DC and RF, with oxygen or nitrogen reactive processes; one DC gun has a source for magnetic targets.
Targets: Ti, W, Fe, Ag, Al, Mo, MgO, WO3, Al2O3, SiO2, undoped Si, Ge2Sb2Te5, Sb2Te3 and GeTe.
Process temperature: Room-temperature and heated recipes; some materials require several hundred degrees.
Conformality: Sidewall coverage; limited coverage inside deep features.
CMOS compatibility: List every existing film, including Au, Cu and polymers; CMOS-clean processing uses a separate material flow.

Resist sidewall coating can leave metal fences or prevent clean lift-off.
Reactive-film composition, stress and electrical properties depend on the selected recipe.
Heat and plasma exposure can damage completed devices; include both exposure limits with the order.
Ultrathin films can be discontinuous or contain pinholes; electrical continuity depends on material and substrate.
Prior Au, Ag or Cu exposure can restrict later clean deposition and etching; list the complete processing history.

04 / 07

PECVD

Plasma-enhanced chemical vapor deposition (PECVD) of silicon oxide, nitride and oxynitride films for insulation and passivation.

Wafer size: Up to 5"
Temperature: 250 – 400 °C
Thickness: 15 nm – 1 µm
Uniformity: < 5 %

Materials

SiOₓ
SiNₓ
SiOₓNᵧ

Materials and thickness

Material	Thickness per run	Use and notes
SiOₓ (silicon oxide)	15 nm – 1 µm	Insulating layer
SiNₓ (silicon nitride)	15 nm – 1 µm	Insulating layer
SiOₓNᵧ (silicon oxynitride)	15 nm – 1 µm	Insulating layer

Full specifications

Substrates: Si, glass, fused silica, sapphire and SiC.
Sample size: Pieces to 5" wafers.
Process temperature: 250–400 °C.
Process temperature: 300 °C is typical for oxide and nitride.
Materials: SiOx, including TEOS oxide; SiNx; SiOxNy.
Film properties: Silicon nitride: refractive index 1.95–2.0, slightly tensile. TEOS oxide: refractive index 1.45–1.5, compressive. Thickness uniformity better than 5 %.
Conformality: Coverage over moderate topography; vertical walls receive thinner coatings than flat surfaces.
CMOS compatibility: List every existing film, including Au, Cu and polymers; CMOS-clean processing uses a separate material flow.

Low-temperature films differ in electrical, optical and stress properties; specify the properties needed for the device.
Deep trenches and vertical walls receive less coverage than planar surfaces.
Fragile membranes and completed devices are sensitive to film stress and plasma exposure.

05 / 07

APCVD

Atmospheric-pressure chemical vapor deposition (APCVD) of undoped and doped oxide glasses for insulation, passivation and planarization.

Wafer size: Up to 6"
Temperature: 350 – 450 °C
Pressure: Atmospheric
Dopants: B, P

Materials

SiO₂ (USG)
PSG
BSG
BPSG

Materials and thickness

Material	Thickness per run	Use and notes
SiO₂ (USG)	50 nm – 2 µm	Undoped oxide
PSG	100 nm – 2 µm	Phosphorus-doped glass Up to 8 wt% P.
BSG	100 nm – 1 µm	Boron-doped glass
BPSG	200 nm – 1.5 µm	Boron- and phosphorus-doped glass Reflows at 850–950 °C.

Full specifications

Substrates: Si, glass, fused silica and sapphire; every existing film must tolerate the deposition temperature.
Sample size: Pieces to 150 mm wafers, carried under the injectors on a heated belt.
Process temperature: 350–450 °C at the wafer.
Pressure: Atmospheric; no vacuum chamber.
Chemistry: Silane and oxygen for fast blanket oxide; TEOS and ozone for conformal coverage and gap fill. Phosphorus and boron sources dope the glass.
Materials: Undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG) and borophosphosilicate glass (BPSG).
Dopants: PSG up to 8 wt% P; BPSG 2–5 wt% B and 3–5 wt% P.
Reflow: Doped glass flows at 850–950 °C to smooth steps; the anneal is a separate step.
Conformality: Silane oxide thins and overhangs at steep steps; TEOS–ozone oxide follows the topography.
CMOS compatibility: List every existing film, including Au, Cu and polymers; CMOS-clean processing uses a separate material flow.

Doped glass takes up moisture; it is annealed or capped soon after deposition.
Glass over aluminum stays at or below 450 °C; reflow needs a stack without aluminum.
Narrow, steep gaps need TEOS–ozone oxide; silane oxide leaves voids in them.

06 / 07

ALD

Atomic layer deposition (ALD) of thin conformal coatings for patterned surfaces and multilayer stacks.

Wafer size: Up to 8"
Sample height: Up to 2 cm
Temperature: Up to 450 °C
Thermal aspect ratio: > 450:1

Materials

Al₂O₃
HfO₂
TiO₂
TiN

Materials and thickness

Material	Thickness per run	Use and notes
Al₂O₃	1–100 nm	Oxide layer Thermal: 100 nm maximum; plasma: 50 nm maximum.
HfO₂	5–100 nm	Oxide layer Thermal: 100 nm; plasma: 50 nm maximum. Some thermal recipes reach 150 nm.
TiO₂	A few nm – 100 nm	Oxide layer Thermal coating; temperature and recipe determine film phase.
TiN	2.5–50 nm	Conductive nitride Unpassivated ultrathin films can have nonlinear electrical behavior.

Full specifications

Substrates: Si, glass, fused silica, sapphire and SiC.
Sample size: Pieces to 8" (200 mm) wafers, up to 2 cm tall.
Process temperature: Substrate temperatures up to 450 °C.
Modes: Thermal continuous mode for faster runs; thermal exposure mode for structures above 450:1; plasma mode for nitrides and metals.
Precursors: Hf, Ti, Al, Ni and Si.
Films: Al2O3, HfO2, TiO2 and TiN.
Conformality: Plasma films are uniform on 20:1 aspect ratios; thermal exposure mode coats structures above 450:1.
CMOS compatibility: List every existing film, including Au, Cu and polymers; CMOS-clean processing uses a separate material flow.

Thermal and plasma-assisted recipes have different temperature ranges and substrate requirements.
Deep recesses can receive incomplete coatings, especially with plasma-assisted processing.
Plasma-sensitive devices require restricted exposure; all substrates must tolerate the selected surface chemistry.
Film stress and run duration limit thicker coatings.

07 / 07

Parylene Coating

Conformal polymer coatings for exposed device surfaces and small components.

Wafer size: Up to 4"
Max thickness: 10 µm
Temperature: Room temperature
Material: Parylene C

Materials

Parylene C

Materials and thickness

Material	Thickness per run	Use and notes
Parylene C	Tens of nm – 10 µm	Conformal polymer film Surface preparation controls adhesion; very thin films provide limited barrier protection.

Full specifications

Substrates: Vacuum-compatible Si, glass, metals, ceramics, polymers and assembled components.
Sample size: Pieces, small components and wafers to 100 mm; component height must fit the chamber.
Process temperature: Room-temperature deposition at the sample.
Materials: Parylene C.
Conformality: Conformal coverage of exposed surfaces; deep cavities and masking edges limit coverage.
Uniformity: Thickness varies with part geometry; specify coating measurement locations.

Adhesion depends on substrate preparation and surface cleanliness.
Connectors, bonding pads and other uncoated surfaces require masking.
Polymer coatings remain permeable and do not provide a hermetic seal.

Materials

Every film, by method.

The thickness each method deposits per run.

Material	E-beam	Thermal	Sputtering	PECVD	APCVD	ALD	Parylene
Metals
Alaluminum	1 nm – 1 µm	1 nm – 1 µm	1–500 nm
Agsilver	1 nm – 1 µm	1–500 nm	1–200 nm
Augold	1–600 nm	1–200 nm
Crchromium	1–300 nm	10–100 nm
Feiron			5–150 nm
Momolybdenum			1–100 nm
Ninickel	1 nm – 1 µm
Ptplatinum	1–600 nm
Tititanium	1 nm – 1 µm		5–150 nm
Wtungsten	1–20 nm		1–600 nm
Alloys
AuPdgold–palladium	On request
FeCoBiron–cobalt–boron	On request
Oxides and glasses
SiO₂silicon oxide			5–150 nm	15 nm – 1 µm	50 nm – 2 µm
PSGphosphosilicate glass					100 nm – 2 µm
BSGborosilicate glass					100 nm – 1 µm
BPSGborophosphosilicate glass					200 nm – 1.5 µm
Al₂O₃aluminum oxide			A few nm – 200 nm			1–100 nm
HfO₂hafnium oxide						5–100 nm
TiO₂titanium oxide						A few nm – 100 nm
MgOmagnesium oxide			On request
WO₃tungsten oxide			5–150 nm
Nitrides
SiNₓsilicon nitride				15 nm – 1 µm
SiOₓNᵧsilicon oxynitride				15 nm – 1 µm
TiNtitanium nitride						2.5–50 nm
Silicon
Siundoped silicon			A few nm – 200 nm
Phase-change
Ge₂Sb₂Te₅germanium antimony telluride			On request
Sb₂Te₃antimony telluride			On request
GeTegermanium telluride			On request
Polymers
Parylene C							Tens of nm – 10 µm

Bars: thickness per run, 1 nm to 10 µm on a log scale.

Methods

Methods side by side.

Method	Films	Coverage	Temperature	Wafer size	Lift-off
Electron-Beam Evaporation	Metals and alloys	Directional	Room temp. – 700 °C	Up to 4"	Yes
Thermal Evaporation	Metals	Directional	No heating	Up to 4"	Yes
Sputtering	Metals, oxides, silicon, phase-change	Coats sidewalls	Room temp. or heated	Up to 4"	Difficult
PECVD	Silicon oxide, nitride, oxynitride	Thinner on walls	250 – 400 °C	Up to 5"	No
APCVD	Undoped and doped oxide glass	Conformal with TEOS–ozone	350 – 450 °C	Up to 6"	No
ALD	Oxides, TiN	Conformal	Up to 450 °C	Up to 8"	Difficult
Parylene Conformal Coating	Parylene C	Conformal, every surface	Room temperature	Up to 4"	No; masked instead

Request a Quote

Tell us what you’re building.

Tell us what you want to make and what it needs to do. Send the substrate, film stack, layout, quantity, and requested timing for a quote.

Substrates and sizes
Film stack and feature sizes
Quantity and timeline