Si microchannel cooling

A cold plate is a solid structure that transfers heat into flowing liquid.² In direct-to-silicon cooling, a separate silicon cold plate bonds to the back of the device, enclosing liquid passages against its surface.^2,4 The active circuitry stays on the opposite face, outside the coolant.^2,5

A conventional lidded package conducts heat through the die, interface materials, lid and cold-plate base before reaching liquid.² A thermal interface material, or TIM, fills gaps between assembled surfaces but adds thermal resistance.² Direct bonding removes the cold-plate TIM, and the silicon cooler can replace the lid and its interfaces.^2,4

Heat crosses the device silicon and enters liquid along the channel roof.^2,7 Heat also spreads through bonded lands into the cap and channel walls, adding wetted area.^1,2,7 The remaining silicon beneath the channel floor provides support; it is outside the direct roof-to-liquid heat path.^2,6

Small channels shorten the distance over which heat diffuses into the moving liquid.¹ For comparable laminar flows, reducing the hydraulic diameter increases the heat-transfer coefficient, which relates heat flux to the wall-to-liquid temperature difference.¹ Hydraulic diameter expresses channel size as four times its cross-sectional area divided by its wetted perimeter.¹

An inlet manifold distributes liquid among the channels, and an outlet manifold collects the warm return flow.⁵ Straight channels can be fed through headers at their ends.^5,7 Distributed manifolds instead feed shorter channel segments, reducing the distance liquid travels through each narrow passage.^5,8

Narrow passages also resist flow, so channel geometry and manifold layout determine both cooling and pressure drop.^7,8 Hydraulic pumping power is pressure drop multiplied by volumetric flow: P = Δp × Q.^7,8 Electrical pump power is higher because the pump and the rest of the loop introduce additional losses.^7,8

Thermal resistance describes temperature rise per unit heat load: R = (T − Tin)/P, in K/W.^1,9 Here T is the device temperature, Tin is inlet coolant temperature, and P is heat load.^1,9 Heat flux is power divided by heated area, so area-normalized resistance uses heat flux instead of power and has units K·cm²/W.^1,9

Silicon microchannel cooling began with channels formed directly in a heated silicon substrate.¹ Microfluidics confines and controls liquid in small channels.^5,8 Later work explored separate coolers, liquid-cooled interposers and cooling integrated into semiconductor packages.^3,9,10 An interposer is an intermediate substrate that carries connections between devices and the package.¹⁰

1. Foundations
2. 1981

   Water cooling in silicon

   Tuckerman and Pease removed 790 W/cm² with a maximum 71 K rise above inlet water, using vertical channels in (110) silicon.¹

3. 2007

   The attachment interface matters

   IBM reported a multipass silicon cooler with epoxy or indium attachment, showing how the interface influences overall thermal resistance.⁹

4. Embedded cooling
5. 2012

   Cooling within and between chips

   DARPA launched the ICECool solicitation for cooling within and between chips, establishing an embedded-cooling research program.¹¹

6. 2015

   Interposers and working logic

   Georgia Tech demonstrated a cooled silicon interposer and separately reported backside liquid cooling of a working logic device.^10,12

7. 2020

   Electronics and fluidics designed together

   EPFL integrated gallium nitride electronics with silicon microfluidics, demonstrating more than 1,700 W/cm² heat removal.⁸ Stanford detailed fabrication of separate large-area cooler and manifold wafers.⁵

8. Package integration
9. 2024

   Kilowatt package cooling

   TSMC reported a silicon-integrated micro-cooler handling a uniform 2,000 W load with 40 °C inlet water.³

10. 2025

    Separate coolers bonded to silicon

    Adeia demonstrated a directly bonded silicon cold plate.² TSMC presented direct-to-silicon cooling integrated on its CoWoS packaging platform.¹³

11. 2026

    Flow distribution and integration

    Research addressed wet-etched cooler integration, partitioned flow and low-pressure manifold cooling.^4,7,14 A fabrication review surveyed wet, dry and hybrid silicon-channel processes.¹⁵

Adeia’s 2025 study directly bonded a separate silicon cold plate to the device.² At 150–200 W/cm² and more than 1,000 W die power, it reported about 70% lower junction-to-inlet resistance than its comparison configuration.² That result includes the benefit of changing the attachment interface.²

The 2026 Adeia manuscript uses computational fluid dynamics, a numerical model of fluid flow and heat transfer, checked against experiments.⁷ Its optimized flow layout reaches 78.4 °C and 8 psi pressure drop, versus 90.8 °C and 25 psi for the baseline.⁷ Those layout comparisons are model results at fixed total flow.⁷

Microsoft reported laboratory microfluidic cooling with up to threefold better heat removal and a 65% reduction in maximum temperature rise in 2025.¹⁶ These company-reported improvements depend on the tested configuration; the percentage describes temperature rise above a reference, not absolute temperature.¹⁶

A meaningful thermal comparison holds inlet temperature, heat load and flow conditions together with the measured pressure drop.^2,7 Peak heat removal and peak cooling efficiency can occur at different operating points.^8,14 Thermal performance and long-term package reliability require separate measurements.^4,16

Glance Foundry wet-etches straight channels in a (100) silicon cap wafer using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).^4,6 The (100) designation identifies the wafer’s crystal plane.⁶ The cap aligns to the device wafer in a mask aligner, with the second wafer held in place of the mask.¹⁷ Radio-frequency (RF) oxygen-plasma activation prepares the surfaces for direct bonding, followed by a low-temperature anneal, or heat treatment.^6,18

The two wafers remain separate through channel etching, port formation and surface preparation.^4,6 This keeps the cap’s hot masking processes and alkaline etchants away from the device circuitry.^5,6,19 The cap’s flat sealing lands then contact the polished device backside to enclose the channels.^2,6

Anisotropic wet etching removes silicon at different rates along different crystal planes.⁶ On a (100) wafer, the slowly etched {111} planes form walls at 54.74° to the wafer surface.⁶ Properly oriented straight openings therefore develop sloped walls and a flat bottom until the opposing walls meet.⁶

For ideal facets, bottom width equals top width minus √2 times depth.⁶ The V-groove limit is top width divided by √2, so a 100 µm opening reaches approximately 70.7 µm depth.⁶ The representative 300 µm opening at 100 µm depth leaves a 158.6 µm floor and 100 µm bonding lands at 400 µm pitch.⁶

KOH and TMAH both form these crystal-defined walls, but bath composition and temperature change their etch rates.^6,21 TMAH avoids introducing potassium; compatibility still depends on the exposed materials.^6,19,21 Mask thickness accounts for the entire channel and port etch, including erosion and defects.^6,20

Corners at headers and channel intersections can undercut faster than long, straight edges.⁶ Sacrificial corner extensions compensate for this retreat, with dimensions established by bath-specific test patterns.⁶ The {111} walls also etch slowly, so a V-groove is only approximately self-limiting.⁶

Bonding lands must remain free of scratches, particles, dried residues and adhesive contact.^4,6 After KOH, an acid-based metal-ion clean addresses potassium contamination before final bonding preparation.^6,24,25 Clean handling and covered storage preserve those surfaces between operations.^4,6

Direct bonding joins prepared surfaces without an adhesive layer.⁶ In this route, the surfaces are hydrophilic, meaning they attract water, and oxygen-plasma treatment creates or modifies their thin surface oxide.^6,18 The resulting silicon-to-silicon assembly can therefore contain oxide at the bonded interface.⁶

Local roughness and wafer shape both affect whether the surfaces make intimate contact.^6,26 Published hydrophilic bonding guidance gives root-mean-square roughness below 0.5 nm, measured with an atomic force microscope.²⁶ Particles can create unbonded regions much larger than themselves, making the final particle, organic and metal-ion clean essential.⁶

Dziuban’s Bonding in Microsystem Technology (2006), pages 151–153, describes oxygen-plasma-assisted silicon-to-silicon bonding well below 300 °C.⁶ Radio-frequency oxygen plasma activates both mating faces before rinsing, drying and contact.¹⁸ Plasma exposure and the later anneal are matched to the device’s surface chemistry, electrical sensitivity and thermal budget.^6,18,27

Gatzen, Saile & Leuthold describe wafer-to-wafer alignment in Micro and Nano Fabrication: Tools and Processes (2015), page 447.¹⁷ A contact/proximity mask aligner uses a bonding fixture to hold the second wafer in the position normally occupied by the mask.¹⁷ Backside or infrared optics register the wafer marks, while clamps and spacers preserve alignment before contact.¹⁷

Infrared alignment views buried marks through silicon, so mark placement must account for metal coverage and wafer transmission.^6,17 The alignment budget includes translation, rotation and movement during clamping or transfer.¹⁷ Registration marks measured after bonding reveal the final offset.¹⁷

Infrared images locate voids, while mechanical tests measure adhesion.^6,18,28 Crack-opening tests on witness wafers estimate interfacial energy in J/m²; tensile tests measure strength in MPa.^6,18 These are distinct measurements, and patterned channels change the bonded area and mechanical response.^6,18

An external manifold connects the cap’s backside ports to the liquid loop.⁴ Its supports carry tubing loads, and coolant-compatible seals contain the flow at each connection.⁴ The manifold’s pressure loss and flow distribution contribute to the assembled cooler’s performance.^4,7

Leak and pressure tests evaluate the complete fluid circuit before powered thermal testing.^4,18 Proof pressure and dwell reflect the intended operating conditions and package strength, while destructive burst tests use sacrificial units.^4,18 Bond imaging alone cannot establish liquid tightness.^6,18

Calibrated heaters and temperature sensors measure the thermal response across inlet temperatures, flow rates and heat loads.^2,5,7 Each operating point records heat input, heated area, inlet and outlet temperatures, peak device temperature, flow and pressure drop.^2,7 Coolant heat pickup provides an energy-balance check against heater power and losses to the surroundings.^2,7

• Thermal record: peak and average temperatures, thermal resistance, heated area and measurement uncertainty at each operating point.^2,7
• Hydraulic record: flow, pressure drop and pumping demand for the assembled cooler and its manifold.^4,7
• Reliability record: leak, thermal and bond-inspection results after pressure cycling, thermal cycling and coolant exposure.^4,16

Filtration, coolant cleanliness and control of trapped gas protect the narrow flow passages.^4,7,10 Continued testing checks for deposits, corrosion, blockage and changes in external seals.^4,16 The operating envelope belongs to the tested combination of channel geometry, bond, coolant and package.^4,16