Layout Intake and Preparation
Layout preparation for fabrication, layer mapping, alignment marks and process-compatible features.
- Contact rules
- 2 µm
- Maskless line size
- 0.6 µm
- Preferred file
- GDSII
- Conversions
- OASIS / DXF / CIF
- GDSII
- OASIS
- DXF
- CIF
- Complete layer stack and material history required
- Electrical design and simulation: separate services
Full specifications
- Files
- GDSII preferred; OASIS/DXF/CIF conversion. Include units, top cell, layer/datatype map and dimensioned PDF.
- Design rules
- Contact exposure: about 2 µm. Maskless writing: lines down to 0.6 µm; spacing and transfer requirements are checked separately.
- Nanoscale layout
- Include critical widths, gaps, exposed area and overlay tolerance.
- Alignment
- Include global/local marks, front/back orientation and a coordinate map.
- Dicing lanes
- Continuous streets with clearance for cutting loss and edge chipping.
- Process temperature
- Include the maximum sample temperature for subsequent processing.
- Incomplete layer stacks and material histories prevent reliable selection of masks and pattern-transfer steps.
- Manufacturability checks cover layout and fabrication constraints; electrical design and device simulation are separate services.