Standard service

Electroplating

Copper, nickel, gold and tin build-up on conductive surfaces, as blanket films or through resist molds. Specify the seed layer, pattern and thickness.

01 / 04

Copper Electroplating

Copper films and resist-defined structures on conductive seed layers.

Wafer size
Up to 4"
Thickness
2 – 30 µm
Temperature
25 °C
Aspect ratio
≤ 15
  • Cu
  • Cr/Cu
  • Continuous seed and electrical contact required
  • Thickness uniformity set by pattern density
  • Thickness limit: mold height; overplating: wider features

Materials and thickness

MaterialThickness per runUse and notes
Cu2–30 µmPlated metal Pattern density and exposed area affect thickness uniformity.
Full specifications
Substrates
Seeded Si, glass, sapphire, ceramics and bath-compatible bulk metals.
Sample size
Pieces to 100 mm wafers with accessible electrical contacts.
Materials
Cu on a continuous conductive seed; Cr/Cu is a seed option.
Process temperature
25 °C.
Thickness range
2–30 µm.
Minimum feature
Minimum feature depends on mold width, depth, spacing and exposed area.
Resolution
Aspect ratio up to 15, depending on mold geometry and exposed area.
CMOS compatibility
Separate metal-processing flow; excluded from front-end CMOS-clean processing.
  • Continuous seed coverage and electrical contact are required across every region to be plated.
  • Pattern density and exposed area affect thickness uniformity.
  • Mold height limits deposit thickness; overplating widens features beyond the mold edge.
  • Exposed seed between features requires removal unless electrical connections are intentional; seed etching must preserve the plated structures.
02 / 04

Nickel Electroplating

Nickel films and resist-defined structures for metal build-up and released parts.

Wafer size
Up to 4"
Thickness
20 – 50 µm
Temperature
≈50 – 55 °C
Seed option
NiV
  • Ni
  • NiV
  • Thickness limits: mold height and film stress
  • High-aspect-ratio molds: limited filling and release
  • Exposed seed removal between isolated features

Materials and thickness

MaterialThickness per runUse and notes
Ni20–50 µmPlated metal Mold height and stress limit thickness.
Full specifications
Substrates
Seeded Si, glass, sapphire, ceramics and bath-compatible bulk metals.
Sample size
Pieces to 100 mm wafers with accessible electrical contacts.
Materials
Ni over a continuous conductive seed; NiV is a seed option.
Process temperature
Approximately 50–55 °C.
Thickness range
20–50 µm.
Minimum feature
Minimum feature depends on mold width, depth, spacing and exposed area.
Film stress
Specify permitted bow or stress for freestanding and membrane-supported parts.
CMOS compatibility
Separate metal-processing flow; excluded from front-end CMOS-clean processing.
  • Mold height limits deposit thickness; overplating widens features beyond the mold edge.
  • Exposed seed between features requires removal unless electrical connections are intentional; seed etching must preserve the plated structures.
  • High aspect-ratio molds limit complete filling and clean release.
  • Film stress and magnetic properties depend on the selected bath and deposition conditions.
03 / 04

Gold Electroplating

Gold build-up for patterned contacts, bonding surfaces and structural layers.

Wafer size
Up to 4"
Thickness
4 – 30 µm
Temperature
50 – 60 °C
Thin features
4 – 5 µm
  • Au
  • Continuous seed and electrical contact required
  • Thickness limit: mold height; overplating: wider features
  • Bonding properties set by deposit composition

Materials and thickness

MaterialThickness per runUse and notes
Au4–30 µmPlated metal Thin structures: 4–5 µm; thicker deposits depend on mold height and geometry.
Full specifications
Substrates
Seeded Si, glass, sapphire, ceramics and bath-compatible bulk metals.
Sample size
Pieces to 100 mm wafers with accessible electrical contacts.
Materials
Au over a continuous metal seed; every plated region requires electrical contact.
Process temperature
50–60 °C.
Thickness range
4–5 µm for thin structures; thicker deposits up to 30 µm.
Minimum feature
Minimum feature depends on mold width, depth, spacing and exposed area.
CMOS compatibility
Separate metal-processing flow; excluded from front-end CMOS-clean processing.
  • Mold height limits deposit thickness; overplating widens features beyond the mold edge.
  • Exposed seed between features requires removal unless electrical connections are intentional; seed etching must preserve the plated structures.
  • Soft pure gold and hardened gold alloys have different bonding properties; specify the required deposit.
  • High aspect-ratio molds limit complete filling and clean release.
04 / 04

Tin Electroplating

Pure tin films and resist-defined solder features.

Wafer size
Up to 4"
Thickness
4 – 6 µm
Seal width
30 – 150 µm
Temperature
Room temperature
  • Sn
  • Au
  • Reflow: separate thermal step
  • Tin whiskers and underlayer compatibility limit reliability
  • Alloy stacks: separate composition and thickness specifications

Materials and thickness

MaterialThickness per runUse and notes
Sn4–6 µmPlated tin layer Patterned tin on a compatible plated underlayer.
Full specifications
Substrates
Seeded Si, glass, sapphire, ceramics and bath-compatible bulk metals.
Sample size
Pieces to 100 mm wafers with accessible electrical contacts.
Materials
Sn over a compatible conductive seed or plated underlayer, including Au.
Process temperature
Room-temperature plating; reflow is a separate thermal step.
Thickness range
4–6 µm.
Minimum feature
Minimum feature depends on mold width, depth, spacing and exposed area.
Resolution
Seal patterns: 30–150 µm wide; minimum feature depends on mold geometry.
CMOS compatibility
Separate metal-processing flow; excluded from front-end CMOS-clean processing.
  • Mold height limits deposit thickness; overplating widens features beyond the mold edge.
  • Exposed seed between features requires removal unless electrical connections are intentional; seed etching must preserve the plated structures.
  • Tin whiskers, storage conditions and underlayer compatibility affect solderability and assembly reliability.
  • Tin alloys and sequential alloy stacks require separate composition and thickness specifications.

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