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Substrate & Wafers

Choose starting wafers and coated substrates, or send your own material for fabrication. Supply the full substrate specification so the process can be matched to it.

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  1. 01Silicon Wafers
  2. 02Silicon with Films and SOI
  3. 03Glass and Quartz Substrates
  4. 04Sapphire Substrates
  5. 05Silicon Carbide and GaN Templates
  6. 06Customer-Supplied Wafers and Pieces
01 / 06

Silicon Wafers

Silicon wafers for device fabrication and process trials.

Diameters
50 / 75 / 100 mm
Prime thick.
380 – 525 µm
Test thick.
525 – 675 µm
High-resist.
>10,000 Ω·cm
  • Si
  • (100)
  • (111)
  • p-type
  • n-type
  • Prime
  • Test
  • SSP
  • DSP
  • Dopant, orientation and polish combinations: lot-specific
  • Test grade: resistivity specified separately
  • 150 mm: compatible equipment required throughout fabrication

Materials and thickness

MaterialThickness per runUse and notes
Silicon, prime grade380–525 µmDevice substrate Specify orientation, dopant, resistivity and polish.
Silicon, test grade525–675 µmProcess trial substrate Specify orientation, dopant, resistivity and polish.
Full specifications
Sample size
50, 75 and 100 mm diameters; 150 mm requires compatible equipment throughout fabrication.
Orientation
(100) and (111); (110) and offcut wafers by special order.
Doping and resistivity
Boron p-type; phosphorus/arsenic/antimony n-type. Resistivity options: 0.001–0.005, 1–10 or >10,000 Ω·cm; specify the lot range.
Surface finish
Single-side or double-side polish; specify active face, thickness, flatness and backside processing.
Grade
Prime for device surfaces; test for process trials. Lot specifications define surface and dimensional tolerances.
Process temperature
Room-temperature handling; subsequent heating specified separately.
  • Available wafer lots determine combinations of dopant, orientation, resistivity and polish.
  • Test grade does not specify electrical resistivity; include the required resistivity range.
02 / 06

Silicon with Films and SOI

Silicon substrates with oxide, nitride or defined silicon-on-insulator layers.

Oxide supply
5 nm – 2 µm
Nitride film
100 nm – 2 µm
SOI device Si
10 – 100 µm
Buried oxide
1 – 2 µm
  • Si
  • SiO₂
  • Nitride
  • SOI
  • Low-stress
  • SOI layer thicknesses fixed by purchased stack
  • Membrane yield limits: nitride stress and pinholes
  • Oxide stripping: exposed intentional oxide loss

Materials and thickness

MaterialThickness per runUse and notes
Thermal SiO₂ on Si5 nm – 2 µmInsulating starting film Specify oxide thickness and supplier tolerance.
Silicon nitride on Si100 nm – 2 µmMask or membrane film Film thickness; specify stress and wafer bow.
SOI10–100 µmDefined device silicon layer Device silicon thickness; specify buried oxide and handle separately.
Full specifications
Materials
Thermal oxide on Si, silicon nitride on Si and SOI.
Sample size
5 × 5 mm pieces to 100 mm wafers; smaller pieces and 150 mm wafers need compatible holders.
Thickness range
Oxide supply: 5 nm–2 µm; dry growth: 5–300 nm; wet growth: up to 2–3 µm.
SOI stack
Device Si: 10–100 µm; buried oxide: 1–2 µm. Specify handle thickness separately.
Film stress
Specify stoichiometric or low-stress nitride and allowable wafer bow.
Process temperature
Supplied without additional heating; new thermal oxide growth requires high-temperature processing.
  • SOI device, buried-oxide and handle thicknesses are fixed by the purchased wafer stack.
  • Nitride stress, thickness and pinholes limit membrane dimensions and yield.
  • Oxide stripping removes exposed intentional oxide and can expose underlying layers.
03 / 06

Glass and Quartz Substrates

Optical and insulating substrates in fused silica and borosilicate glass.

Routine wafer
≤ 100 mm
Silica thick.
475 – 575 µm
Boro. thick.
145 – 500 µm
Boro. long-use
450 °C
  • Fused silica
  • Borosilicate
  • Quartz
  • HF attack on silica substrates
  • Electron-beam patterning: charge control required
  • Thermal limits set by glass grade and film stack

Materials and thickness

MaterialThickness per runUse and notes
Fused silica475–575 µmOptical or insulating substrate Substrate thickness; specify optical grade and polished faces.
Borosilicate glass145–500 µmInsulating substrate Nominal substrate thickness varies by grade; specify thermal limits.
Full specifications
Materials
Fused silica, borosilicate and explicitly specified crystalline quartz.
Sample size
5 × 5 mm pieces to 100 mm wafers; smaller pieces and 150 mm wafers need compatible holders.
Surface finish
Specify thickness, polished faces, flatness and optical transmission.
Process temperature
Borosilicate grade-dependent limits: 450 °C long-term; 500 °C short-term. Supplied without heating.
CMOS compatibility
Glass composition and prior metals can exclude samples from clean semiconductor processing.
  • HF-based oxide removal attacks silica substrates; protect optical faces and dimensional features.
  • Insulating substrates require charge control for electron-beam lithography.
  • Thermal limits differ between borosilicate and fused silica; the glass grade and complete film stack set the allowable temperature.
04 / 06

Sapphire Substrates

Polished sapphire for electrically insulating crystalline substrates.

Wafer sizes
50 / 100 mm
Thickness
330 – 430 µm
Orientation
c-plane
Polish
Single / double
  • Sapphire
  • Al₂O₃
  • c-plane
  • Electron-beam patterning: charge control required
  • Dicing: suitable blade and edge-chipping allowance

Materials and thickness

MaterialThickness per runUse and notes
Sapphire330–430 µmInsulating crystalline substrate Nominal substrate thickness; specify orientation, polish and offcut.
Full specifications
Materials
Single-crystal alumina; c-plane and other specified orientations.
Sample size
Pieces and 50 or 100 mm wafers; other sizes need compatible holders.
Surface finish
Single-side or double-side polish; specify roughness, thickness and offcut.
Process temperature
Supplied without heating; film stack and process atmosphere limit subsequent temperatures.
CMOS compatibility
Material history determines access to clean furnaces and shared semiconductor processing.
  • Insulating sapphire requires charge control for electron-beam patterning.
  • Hard, brittle sapphire requires a suitable dicing blade and allowance for edge chipping.
05 / 06

Silicon Carbide and GaN Templates

SiC wafers and GaN templates as starting materials for fabrication.

Wafer sizes
50 / 100 mm
SiC thickness
350 – 500 µm
GaN thickness
1 – 5 µm
SiC polytype
4H-SiC
  • 4H-SiC
  • GaN
  • Sapphire
  • Stack-specific etch and thermal requirements
  • Prior metals: segregated processing
  • Insulating grades: electron-beam charge control required

Materials and thickness

MaterialThickness per runUse and notes
Conductive 4H-SiC350–500 µmStarting wafer Nominal substrate thickness; specify electrical properties, offcut and surface finish.
Semi-insulating 4H-SiC350–500 µmStarting wafer Nominal substrate thickness; specify electrical properties, offcut and surface finish.
GaN template1–5 µmPre-grown compound-semiconductor layer GaN layer thickness; specify the supporting substrate and buffer layers.
Full specifications
Materials
Conductive or semi-insulating 4H-SiC; GaN on sapphire or SiC.
Sample size
Pieces and 50 or 100 mm wafers; 150 mm requires compatible equipment throughout fabrication.
GaN stack
GaN: 1–5 µm; specify substrate, polarity, doping, buffers and thickness tolerance.
SiC specification
Specify polytype, conductivity, offcut, polished face and epitaxial layers.
Process temperature
Supplied without heating; subsequent high-temperature steps require suitable atmosphere and surface protection.
  • Compound-semiconductor buffers, contacts and substrates have different etch and thermal requirements.
  • Prior metals and buffer layers can require segregated processing; list the complete stack and material history.
  • Insulating grades require charge control during electron-beam patterning.
06 / 06

Customer-Supplied Wafers and Pieces

Fabrication on customer-supplied wafers and pieces.

Routine piece
≥ 5 × 5 mm
Routine wafer
≤ 100 mm
Layer stack
Full disclosure
Thermal limit
Customer-specified
  • Si
  • Coated Si
  • Glass
  • Fused silica
  • Sapphire
  • Unknown films and undeclared adhesives: processing exclusion
  • Loose particles and cracked pieces: processing exclusion
  • Prior gold exposure: segregated processing
Full specifications
Substrates
Si, coated Si, glass, fused silica, sapphire and compound-semiconductor samples.
Sample size
5 × 5 mm pieces to 100 mm wafers; smaller pieces and 150 mm wafers need compatible holders.
Sample condition
Include dimensions, thickness, bow, edge condition, polished faces and fragile or released structures.
Material history
List exposed/buried layers, adhesives, backside films, prior metals and previous processing.
Process temperature
State maximum temperature and duration, plus air-, water-, solvent- or vacuum-sensitive features.
  • Each fabrication step must accommodate the complete substrate and film stack.
  • Unknown films, loose particles, cracked pieces and undeclared adhesives prevent safe processing.
  • Prior gold and other contaminating metals can require segregated processing even after visible films are removed.

Request a Quote

Tell us what you’re building.

Tell us what you want to make and what it needs to do. Send the substrate, film stack, layout, quantity, and requested timing for a quote.

  • Substrates and sizes
  • Film stack and feature sizes
  • Quantity and timeline